The invention provides a memory device, in particular to a non-volatile, resistively switching memory device such as a Phase Change Random Access Memory (“PCRAM”), Conductive Bridging Random Access Memories (“CBRAMs”), and a Magnetoresistive Random Access Memory (“MRAM”). The invention further relates to a method of operating a memory device, in particular a resistively switching memory device.
In the case of conventional memory devices, in particular conventional semiconductor memory devices, one differentiates between functional memory devices (e.g., PLAs, PALs, etc.), and table memory devices, e.g., ROM devices (ROM=Read Only Memory—in particular PROMs, EPROMs, EEPROMs, flash memories, etc.), and RAM devices (RAM=Random Access Memory—in particular e.g., DRAMs and SRAMs).
A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address later. In the case of SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist e.g., of few, for instance 6, transistors, and in the case of DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitive element.
Furthermore, “resistive” or “resistively switching” memory devices have also become known recently, e.g., Phase Change Random Access Memories (“PCRAMs”), Conductive Bridging Random Access Memories (“CBRAMs”), Magnetoresistive Random Access Memories (“MRAM”) etc., etc.
In the case of “resistive” or “resistively switching” memory devices, an “active” or “switching active” material—which is, for instance, positioned between two appropriate electrodes—is placed, by appropriate switching processes, in a more or less conductive state (wherein e.g., the more conductive state corresponds to a stored logic “One”, and the less conductive state to a stored logic “Zero”, or vice versa).
In the case of Phase Change Random Access Memories (PCRAMs), for instance, an appropriate chalcogenide or chalcogenide compound material may be used as a “switching active” material (e.g., a Ge—Sb—Te (“GST”) or an Ag—In—Sb—Te compound material, etc.). The chalcogenide compound material is adapted to be placed in an amorphous, i.e. a relatively weakly conductive, or a crystalline, i.e. a relatively strongly conductive state by appropriate switching processes (wherein e.g., the relatively strongly conductive state may correspond to a stored logic “One”, and the relatively weakly conductive state may correspond to a stored logic “Zero”, or vice versa). Phase change memory cells are, for instance, known from G. Wicker, “Nonvolatile, High Density, High Performance Phase Change Memory”, SPIE Conference on Electronics and Structures for MEMS, Vol. 3891, Queensland, 2, 1999, and e.g., from Y. N. Hwang et al., “Completely CMOS Compatible Phase Change Nonvolatile RAM Using NMOS Cell Transistors”, IEEE Proceedings of the Nonvolatile Semiconductor Memory Workshop, Monterey, 91, 2003, S. Lai et al., “OUM-a 180 nm nonvolatile memory cell element technology for stand alone and embedded applications”, IEDM 2001, Y. Ha et al., “An edge contact type cell for phase change RAM featuring very low power consumption”, VLSI 2003, H. Horii et al., “A novel cell technology using N-doped GeSbTe films for phase change RAM”, VLSI 2003, Y. Hwang et al., “Full integration and reliability evaluation of phase-change RAM based on 0.24 μm-CMOS technologies”, VLSI 2003, and S. Ahn et al., “Highly Manufacturable High Density Phase Change Memory of 64 Mb and beyond”, IEDM 2004, etc.
In the case of the above Conductive Bridging Random Access Memories (CBRAMs), the storing of data is performed by use of a switching mechanism based on the statistical bridging of multiple metal rich precipitates in the “switching active” material. Upon application of a write pulse (positive pulse) to two respective electrodes in contact with the “switching active” material, the precipitates grow in density until they eventually touch each other, forming a conductive bridge through the “switching active” material, which results in a high-conductive state of the respective CBRAM memory cell. By applying a negative pulse to the respective electrodes, this process can be reversed, hence switching the CBRAM memory cell back in its low-conductive state. Such memory components are e.g., disclosed in Y. Hirose, H. Hirose, J. Appl. Phys. 47, 2767 (1975), T. Kawaguchi et. al., “Optical, electrical and structural properties of amorphous Ag—Ge—S and Ag—Ge—Se films and comparison of photoinduced and thermally induced phenomena of both systems”, J. Appl. Phys. 79 (12), 9096, 1996, M. Kawasaki et. al., “Ionic conductivity of Agx(GeSe3)1-x (0<x0.571) glasses”, Solid State Ionics 123, 259, 1999, etc.
Correspondingly similar as is the case for the above PCRAMs, for CBRAM memory cells an appropriate chalcogenide or chalcogenid compound (for instance GeSe, GeS, AgSe, CuS, etc.) may be used as “switching active” material.
In the case of PCRAMs, in order to achieve, with a corresponding PCRAM memory cell, a change from the above-mentioned amorphous, i.e. a relatively weakly conductive state of the switching active material, to the above-mentioned crystalline, i.e. a relatively strongly conductive state of the switching active material, an appropriate relatively high heating current pulse has to be applied to the electrodes, the heating current pulse resulting in that the switching active material is heated beyond the crystallization temperature and crystallizes (“writing process”).
Vice versa, a change of state of the switching active material from the crystalline, i.e. a relatively strongly conductive state, to the amorphous, i.e. a relatively weakly conductive state, may, for instance, be achieved in that—again by means of an appropriate (relatively high) heating current pulse—the switching active material is heated beyond the melting temperature and is subsequently “quenched” to an amorphous state by quick cooling (“erasing process”).
Typically, the above erase or write heating current pulses are provided via respective source lines and bit lines, and respective FET or bipolar access transistors associated with the respective memory cells, and controlled via respective word lines.
As the above, typically a switching of one cell between two states (“high” and “low”, or “zero” and “one”) is performed. In fact, all commercially available computer systems employ this scheme. Still, it is possible for resistively switching memory device that each cell may have more that two states (so called ‘multi-level technologies’). In the following, to apply common notation, memory cells with a number i of possible distinct states are called i-level memory cells. Memory cells with four levels per cell are described in DE 3531580 A1 and EP 007 28 45 A2. However, in these documents, the four levels of this cell are used to be mapped to a common (‘digital’) two-state logic which is comparatively easy because of the same power base of 2.
A practical problem is that it is not always possible to practically realize 2n being a non-zero integer) levels of a cell because, e.g., of a too small sense margin or too small a write margin which prevents reliably sensing or writing, resp., these states.
This, up to now, gives a situation that a cell having three usable levels/states (e.g., a fourth level/state cannot be reliably used because of a too small sense margin and/or a too small a write margin) will only use two of these levels because three levels cannot be matched to the usual logic of base 2. Thus, the potential of the third level is unused what leads to a waste of silicon area. In general, this problem occurs for all cells with a number of levels that are not to the base of 2, e.g., 3, 5, 6, 7, 9 etc.
There exist a need to be able to use memory cells with a number of levels that are not to the base of 2.
For these and other reasons, there is a need for the present invention.